So far we've been working with the same RS latch and all its limitations, such as the forbidden combination of inputs. By providing additional input logic and merging the control signals we have a more robust latch that is less prone to the unstable conditions of the simple RS latch.
For this new latch, the set and reset control signals are merged into one, the data signal. To control the flip flop with only one signal, we have to make sure that the latch is set when the data signal goes high (set to 1) and reset when it goes low (set to 0).
With only one signal this task is easily accomplished with an inverter gate. The non inverted signal will go to the set input and the inverted signal goes to the reset input. The enable circuitry goes after this new input logic to make sure that when the latch is not enabled it will maintain its current state, which would not be possible without this interface logic (one signal would always be high due to the inverter).
This simple arrangement of input logic combined with a two gate latch make it a very popular choice for high density Integrated Circuits (IC's). Sometimes the IC's whole memory and sequential logic is implemented using only latches very similar to these.