Most situations need a counter that outputs only one value per transition, or in other terms, that all outputs change at the same time. In a ripple counter, when two or more bits need to change to reach the final output, intermediate outputs are generated, which can interfere with the correct function of other circuits that depend on the counter.
To overcome this limitation, the same clock signal applied to every flip flop to ensure that they all transition at the same time. The flip flop control signals now need some external logic to set them in the correct level for them to switch to the needed state.
The logic is simple: if all the previous flip flops are 1, then toggle the state (if 1, go to 0; if 0, go to 1). This is easily accomplished with an AND gate with N inputs where N is the number of previous flip flops, or its equivalent "cascaded" AND gates (one extra AND for every extra input, the output of a previous goes to an input of the next gate), which output will be connected to both J and K inputs in a JK flip flop, or adding an extra AND gate whose input is connected to the inverted output of the D flip flop.
The second flip flop is a special case, since there is only one previous flip flop to check, no logic is needed because it can be driven directly by the first flip flop's output.