A good way to overcome this is by connecting two of these transparent latches in what is called a master slave configuration in which one latch is active during the high level of the enable signal and a second, which gets its input from the first, gets activated with the low level of the enable signal.
The latches themselves are not changed in any way, only the enable signal will be connected in a special way: the first gets the signal directly and the second gets an inverted version of it.
When the enable signal is low, the first latch is disabled by the control logic, so it holds its state (no change at the output). At the same time, the second latch is enabled by the inverted signal (~0 = 1) and so its output is the same as its data input, which is connected to the first latch. Since the first latch is not changing at this point, the output of the second latch will not change either.
The moment the enable signal goes high, the first latch is enabled and its input will be the same as its data signal due to the input logic used to overcome the forbidden combination. The second latch is at the same time disabled by the inverted enable signal (~1 = 0), so even when its data input changes due to the first latch changing its output, the final output of this configuration will not change.
As the enable signal falls back to a low level (goes to 0), the first latch gets disabled and holds the last bit of data it got, while the second now gets enabled and starts transferring its data input, which is connected to the output of the first latch, to its output. It is at this point where any data applied through the cycle gets its transfer to the final output of the circuit.
A master-slave latch, commonly known as flip-flop, is an edge triggered device, meaning that it will only perform its full function when the signal changes instead of using a signal level. In this example the D flip-flop is falling edge triggered, since the output only changes when the enable (or more commonly known as clock in edge triggered circuits) goes from high (1) to low (0).
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