The RS Latch
A basic latch can be built with two NOR gates, with the output of one to one of the inputs of the other. The free input on both gates are used as control signals, one to SET the output to 1, and the other to RESET the output to 0. When no control signal is applied, the latch keeps its previous state via the conditions set at the output being fed back as inputs, which result in a condition that keeps the output the same.
The way in which the gates are wired make the output of one gate being the non inverted output of the latch, and the other being the inverted output.
There's one combination that will break that relation: when both Set and Reset are 1, both outputs will be at a 0 level. This in itself is not a cause for major concern, but when we make both control signals go from high to low at the same time, a race condition occurs.
This is called race condition because the output depends on which of the control signals stay high longer will determine the latch's output. If the set signal goes to 0 first, then the latch will have a 0 output (Reset), if the reset signal goes to 0 first, then the latch will have a 1 output (set).
The combination that produces this behavior is called a restricted or forbidden combination, because there's no way to actually know which signal will end up designating the latches output, which is not very good in a logic design where everything is supposed to be in one state or the other with full certainty.
This kind of latch is called a transparent latch because there are no synchronization or enabling signals, which means that the output will change as soon as the signals make it change; the latch doesn't restrict the flow of data through it.
Controlling the latch: Level Gated Latch
One way to have better control over the functioning of the latch, a layer of AND gates are connected between the control signals and the actual latch's gates inputs. One of the AND inputs is shared and is connected to a new control signal: the enable signal.
This new signal controls the availability of the set and reset inputs to the actual latch. When the enable signal is 0, no matter what the set and reset signals are, the latch will never receive them, only 0 will appear since it is connected at the AND gate's outputs, so it will only hold its previous state.
When the enable signal is at 1, the output of the AND gates will depend on the set and reset signals, essentially letting them pass through to the latch. As you can see, this new layer of gates and a new signal allow us to control whether we want the the latch to function (enable it) or to just keep its previous state (when enable = false )
This kind of enable mechanism is called level gating, since the control signals will only reach the latch when the gates it needs to pass are enabled by the level of the enable signal.
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